The invention disclosed herein relates generally to electronic packages and more specifically to an electronic package with an integrated capacitor.
Electronic packages facilitate the mounting and handling of electronic devices such as microprocessors, video controllers and memory. Tape ball grid array packages (hereinafter referred to as TBGA packages) take advantage of the fine line capability of flexible circuit technology and offer superior wiring density and wire bond solder pad density when compared to many other types of electronic package constructions. However, because of the single layer architecture in current TBGA packages, power and ground distribution capability is limited when compared with multi-layer plastic and ceramic ball grid array packages.
Capacitors are used to decouple the system-level power supply from individual electrical devices of an electronic package. Decoupling of an electronic device from the power supply reduces the overall noise in the power distribution network of the electronic package. However, due to increases in the speed and electrical current associated with high-speed electronic devices, traditional capacitor structures do not provide adequate performance because the inductance associated with these types of capacitors inhibits their operation at high speeds. Interconnect inductance in an electronic package chokes the capacitor, preventing the high-speed transfer of electrical current to and from the capacitor.
Embedding capacitors directly into the electronic packages provides significant decoupling capacitance with very low interconnect inductance. Furthermore, the electrodes of the capacitor may serve as reference voltage planes in the electronic package for providing excellent power distribution within the package. This approach facilitates very high-speed operation of electronic devices within an electronic package.
U.S. Pat. No. 4,945,399 discloses a pin grid array package having an integrated, distributed capacitor. The package includes a circuit having two metal layers with a dielectric layer between them. A first one of the metal layers includes signal traces and an electrode. A second one of the metal layer serves as a second electrode. A capacitor is formed in areas where the electrodes of the first and second metal layers overlap. Pins are situated within apertures that extend through the various layers of the circuit, including the electrodes. The area of the first metal layer of the circuit is divided between signal routing and electrode regions, limiting the capacitance of the capacitor. A pin grid array package of this construction is expensive to manufacture. Also, due to the pins breaching the electrode layers, this type of configuration reduces the available capacitance for a given size package.
U.S. Pat. No. 5,027,253 to Lauffer et al discloses a multi-layer circuit package having an embedded thin film capacitor. The package includes at least two signal cores with each one of the cores being interconnected to a corresponding electrode of the capacitor. In this manner, the signal cores are capacitively coupled to each other. The capacitor structure disclosed in this reference does not address decoupling of the power supply from a semiconductor device in the electronic package. Furthermore, because a ground core lies between the capacitor and the semiconductor device, substantially long conductive lead wires and conductive through holes extending through the power core are required to connect the semiconductor device to the electrodes. The length of these lead wires increase inductance, thereby reducing the electrical performance improvements provided by the capacitor.
The requirement of controlling the electrical characteristics of electronic packages is becoming more critical as the operating speed of electronic devices increases. The inability of an electronic package to meet the required electrical current demands of an electronic device results in noise associated with voltage drops within the electronic package. The use of capacitors in electronic packages is known in the art to ameliorate power and ground distribution noise in conventional electronic package configurations. However, prior solutions for using capacitors to reduce noise in electronic packages and prior capacitor designs have provided only limited success for use with high-speed electronic devices in electronic packages. Prior solutions are also limited in their ability to cost effectively provide a low impedance power distribution structure in TBGA cavity-down wire bond electronic packages.
Accordingly, what is needed is an circuit assembly construction that offers an economical and versatile noise reduction solution for high-speed devices of electronic packages that overcomes the shortcomings of previous solutions.